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Freescale Semiconductor Advance Information
Document Number: MC33883 Rev 9.0, 1/2007
H-Bridge Gate Driver IC
The 33883 is an H-bridge gate driver (also known as a full-bridge pre-driver) IC with integrated charge pump and independent highand low-side gate driver channels. The gate driver channels are independently controlled by four separate input terminals, thus allowing the device to be optionally configured as two independent high-side gate drivers and two independent low-side gate drivers. The low-side channels are referenced to ground. The high-side channels are floating. The gate driver outputs can source and sink up to 1.0 A peak current pulses, permitting large gate-charge MOSFETs to be driven and/or high Pulse Width Modulation (PWM) frequencies to be utilized. A linear regulator is incorporated, providing a 15 V typical gate supply to the low-side gate drivers. Features * * * * * * * * * * VCC Operating Voltage Range from 5.5 V up to 55 V VCC2 Operating Voltage Range from 5.5 V up to 28 V CMOS / LSTTL Compatible I / O 1.0 A Peak Gate Driver Current Built-In High-Side Charge Pump Undervoltage Lockout (UVLO) Overvoltage Lockout (OVLO) Global Enable with <10 A Sleep Mode Supports PWM up to 100 kHz Pb-Free Packaging Designated by Suffix Code EG
DW SUFFIX EG SUFFIX (PB-FREE) 98ASB42343B 20-TERMINAL SOICW
33883
H-BRIDGE GATE DRIVER IC
ORDERING INFORMATION
Device MC33883DW/R2 - 40C to 125C MCZ33883EG/R2 20 SOICW Temperature Range (TA) Package
VBAT VBOOST
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VCC VCC2 G_EN C1 C2 MCU CP_OUT LR_OUT GATE_HS1 SRC_HS1 GATE_LS1 GATE_HS2 SRC_HS2 IN_HS1 GATE_LS2 IN_LS1 IN_HS2 /2 IN_LS2 GND_A GND DC Motor
Figure 1. 33883 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
C1 VCC, VCC2 Undervoltage/Overvoltage VCC VCC VDD EN GND G_EN
GND2 VCC2
C2 VCC2
C1 Charge Pump C2 VPOS CP_OUT VDD +5.0 V EN Linear GND Reg +14.5 V LR_OUT VCC2 VCC
VCC2
VCC CP_OUT
LR_OUT
GND_A
GND2
HIGH- AND LOW-SIDE CONTROL WITH CHARGE PUMP
BRG_EN IN_HS1
TSD1
VCC
CP_OUT
OU
Control and Logic
VDD / VPOS Level Shift
Pulse Generator
IN Output
Driver
GATE_HS SRC_HS1
HIGH-SIDE CHANNEL BRG_EN IN_LS1
TSD1
TSD1 Thermal Shutdown
Control and Logic
LR_OUT
VDD / VCC Level Shift Pulse Generator IN Output
Driver
OU
GATE_LS1
LOW-SIDE CHANNEL
GND1
BRG_EN IN_HS2
TSD2
VCC
CP_OUT
OU
Control and Logic
VDD / VPOS Level Shift
Pulse Generator
IN Output
Driver
GATE_HS SRC_HS2
HIGH-SIDE CHANNEL BRG_EN IN_LS2
TSD2
TSD2 Thermal Shutdown
Control and Logic
LR_OUT
VDD / VCC Level Shift Pulse Generator IN Output
Driver
OU
GATE_LS2
LOW-SIDE CHANNEL
GND2
GND
GND
GND_
Figure 2. 33883 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
VCC
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
G_EN SRC_HS2 GATE_HS2 IN_HS2 IN_LS2 GATE_LS2 GND2 C1 GND_A VCC2
C2
CP_OUT SRC_HS1 GATE_HS1 IN_HS1 IN_LS1 GATE_LS1 GND1 LR_OUT
Figure 3. 33883 20-SOICW Terminal Connections Table 1. 20-SOICW Terminal Definitions A functional description of each terminal can be found in the FUNCTIONAL TERMINAL DESCRIPTION section beginning on page 10.
Terminal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Terminal Name VCC C2 CP_OUT SRC_HS1 GATE_HS 1 IN_HS1 IN_LS1 Formal Name Supply Voltage 1 Charge Pump Capacitor Charge Pump Out Source 1 Output High Side Gate 1 Output High Side Input High Side 1 Input Low Side 1 Device power supply 1. External capacitor for internal charge pump. External reservoir capacitor for internal charge pump. Source of high-side 1 MOSFET Gate of high-side 1 MOSFET. Logic input control of high-side 1 gate (i.e., IN_HS1 logic HIGH = GATE_HS1 HIGH). Logic input control of low-side 1 gate (i.e., IN_LS1 logic HIGH = GATE_LS1 HIGH). Gate of low-side 1 MOSFET. Device ground 1. Output of internal linear regulator. Device power supply 2. Device analog ground. External capacitor for internal charge pump. Device ground 2. Gate of low-side 2 MOSFET. Logic input control of low-side 2 gate (i.e., IN_LS2 logic HIGH = GATE_LS2 HIGH). Logic input control of high-side 2 gate (i.e., IN_HS2 logic HIGH = GATE_HS2 HIGH). Gate of high-side 2 MOSFET. Source of high-side 2 MOSFET. Logic input Enable control of device (i.e., G_EN logic HIGH = Full Operation, G_EN logic LOW = Sleep Mode). Definition
GATE_LS1 Gate 1 Output Low Side GND1 LR_OUT VCC2 GND_A C1 GND2 Ground 1 Linear Regulator Output Supply Voltage 2 Analog Ground Charge Pump Capacitor Ground 2
GATE_LS2 Gate 2 Output Low Side IN_LS2 IN_HS2 GATE_HS 2 SRC_HS2 G_EN Input Low Side 2 Input High Side 2 Gate 2 Output High Side Source 2 Output High Side Global Enable
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Rating ELECTRICAL RATINGS Supply Voltage 1 Supply Voltage 2 (1) Linear Regulator Output Voltage High-Side Floating Supply Absolute Voltage High-Side Floating Source Voltage High-Side Source Current from CP_OUT in Switch ON State High-Side Gate Voltage High-Side Gate Source Voltage
(2)
Symbol
Value
Unit
VCC VCC2 VLR_OUT VCP_OUT VSRC_HS IS VGATE_HS VGATE_HS VSRC_HS VCP_OUT VGATE_HS VGATE_LS VG_EN VIN VC1 VC2
-0.3 to 65 -0.3 to 35 -0.3 to 18 -0.3 to 65 -2.0 to 65 250 -0.3 to 65 -0.3 to 20
V V V V V mA V V
High-Side Floating Supply Gate Voltage
-0.3 to 65
V
Low-Side Gate Voltage Wake-Up Voltage Logic Input Voltage Charge Pump Capacitor Voltage Charge Pump Capacitor Voltage ESD Voltage
(3)
-0.3 to 17 -0.3 to 35 -0.3 to 10 -0.3 to VLR_OUT -0.3 to 65
V V V V V V
Human Body Model on All Pins (VCC and VCC2 as Two Power Supplies) Machine Model Notes 1. VCC2 can sustain load dump pulse of 40 V, 400 ms, 2.0 . 2. 3.
VESD1 VESD2
1500 130
In case of high current (SRC_HS >100 mA) and high voltage (>20 V) between GATE_HSX and SRC_HS an external zener of 18 V is needed as shown in Figure 14. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ).
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Rating Power Dissipation and Thermal Characteristics Maximum Power Dissipation @ 25C Thermal Resistance (Junction to Ambient) Operating Junction Temperature Storage Temperature Peak Package Reflow Temperature During Reflow (4), (5) PD RJA TJ TSTG TPPRT 1.25 100 -40 to 150 -65 to 150 Note 5 W C / W C C C Symbol Value Unit
Notes 4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 5. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic OPERATING CONDITIONS Supply Voltage 1 for Output High-Side Driver and Charge Pump Supply Voltage 2 for Linear Regulation High-Side Floating Supply Absolute Voltage VCC VCC2 VCP_OUT 5.5 5.5 VCC+4 - - - 55 28 VCC + 11 but < 65 V V V Symbol Min Typ Max Unit
LOGIC Logic 1 Input Voltage (IN_LS and IN_HS) Logic 0 Input Voltage (IN_LS and IN_HS) Logic 1 Input Current VIN = 5.0 V Wake-Up Input Voltage (G_EN) Wake-Up Input Current (G_EN) VG_EN = 14 V Wake-Up Input Current (G_EN) VG_EN = 28 V LINEAR REGULATOR Linear Regulator VLR_OUT @ VCC2 from 15 V to 28 V, ILOAD from 0 mA to 20 mA VLR_OUT @ ILOAD = 20 mA VLR_OUT @ ILOAD = 20 mA, VCC2 = 5.5 V, VCC = 5.5 V CHARGE PUMP Charge Pump Output Voltage, Reference to VCC VCC = 12 V, ILOAD = 0 mA, CCP_OUT = 1.0 F VCC = 12 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 F VCC2 = VCC = 5.5 V, ILOAD = 0 mA, CCP_OUT = 1.0 F VCC2 = VCC = 5.5 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 F VCC = 55 V, ILOAD = 0 mA, CCP_OUT = 1.0 F VCC = 55 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 F Peak Current Through Pin C1 Under Rapidly Changing VCC Voltages (see Figure 13, page 17) Minimum Peak Voltage at Pin C1 Under Rapidly Changing VCC Voltages (see Figure 13, page 17) IC1 -2.0 VC1MIN -1.5 - - - 2.0 V VCP_OUT 7.5 7.0 2.3 1.8 7.5 7.0 - - - - - - - - - - - - A V VLR_OUT 12.5 VCC2 - 1.5 4.0 - - - 16.5 - - V IG_EN2 - - 1.5 VG_EN IG_EN - 200 500 mA VIH VIL IIN+ 200 4.5 - 5.0 1000 VCC2 V A 2.0 - - - 10 0.8 V V A
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SUPPLY VOLTAGE Quiescent VCC Supply Current VG_EN = 0 V and VCC = 55 V VG_EN = 0 V and VCC = 12 V Operating VCC Supply Current (6) VCC = 55 V and VCC2 = 28 V VCC = 12 V and VCC2 = 12 V Additional Operating VCC Supply Current for Each Logic Input Terminal Active VCC = 55 V and VCC2 = 28 V (7) Quiescent VCC2 Supply Current VG_EN = 0 V and VCC = 12 V VG_EN = 0 V and VCC = 28 V Operating VCC2 Supply Current (6) VCC = 55 V and VCC2 = 28 V VCC = 12 V and VCC2 = 12 V Additional Operating VCC2 Supply Current for Each Logic Input Terminal Active VCC = 55 V and VCC2 = 28 V (7) Undervoltage Shutdown VCC Undervoltage Shutdown VCC2 (8) Overvoltage Shutdown VCC Overvoltage Shutdown VCC2 OUTPUT Output Sink Resistance (Turned Off) Idischarge LSS = 50 mA , VSRC_HS = 0 V (8) Output Source Resistance (Turned On) Icharge HSS = 50 mA, VCP_OUT = 20 V
(8)
Symbol
Min
Typ
Max
Unit
IVCCSLEEP - - IVCCOP - - IVCCLOG - - 5.0 2.2 0.7 - - - - 10 10
A
mA
mA
IVCC2SLEEP - - IVCC2OP - - IVCC2LOG - UV UV2 OV OV2 4.0 4.0 57 29.5 - 5.0 5.0 61 31 5.0 5.5 5.5 65 35 - - 12 9.0 - - 5.0 5.0
A
mA
mA
V V V V
RDS - RDS - ICHARGE HSS - VMAX - - 18 100 200 - 22 - 22
Charge Current of the External High-Side MOSFET Through GATE_HSn Terminal (9) Maximum Voltage (VGATE_HS - VSRC_HS) INH = Logic 1, ISmax = 5.0 mA Notes 6. Logic input terminal inactive (high impedance). 7. 8. 9.
mA
V
High-frequency PWM-ing ( 20 kHz) of the logic inputs will result in greater power dissipation within the device. Care must be taken to remain within the package power handling rating. The device may exhibit predictable behavior between 4.0 V and 5.5 V. See Figure 5, page 12, for a description of charge current.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 7.0 V VSUP 18 V, -40C TA 125C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic TIMING CHARACTERISTICS Propagation Delay High Side and Low Side CLOAD = 5.0 nF, Between 50% Input to 50% Output Turn-On Rise Time CLOAD = 5.0 nF, 10% to 90% Turn-Off Fall Time CLOAD = 5.0 nF, 10% to 90% 10. 11.
(10) (11) (10) (11) (10)
Symbol
Min
Typ
Max
Unit
tPD (see Figure 4) tR - 200 300
ns
ns - 80 180 ns - 80 180
,
(see Figure 4) tF
,
(see Figure 4)
CLOAD corresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side. Rise time is given by time needed to change the gate from 1.0 V to 10 V (vice versa for fall time).
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Analog Integrated Circuit Device Data Freescale Semiconductor
TIMING DIAGRAMS
TIMING DIAGRAMS
50% IN_HS or IN_LS GATE_HS or GATE_LS
t pd t pd
50%
50%
tf tr
50% 10% 90% 90% 10%
Figure 4. Timing Characteristics
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33883 is an H-bridge gate driver (or full-bridge predriver) with integrated charge pump and independent highand low-side driver channels. It has the capability to drive large gate-charge MOSFETs and supports high PWM frequency. In sleep mode its supply current is very low.
FUNCTIONAL TERMINAL DESCRIPTION SUPPLY VOLTAGE TERMINALS (VCC AND VCC2)
The VCC and VCC2 terminals are the power supply inputs to the device. VCC is used for the output high-side drivers and the charge pump. VCC2 is used for the linear regulation. They can be connected together or independent with different voltage values. The device can operate with VCC up to 55 V and VCC2 up to 28 V. The VCC and VCC2 terminals have undervoltage (UV) and overvoltage (OV) shutdown. If one of the supply voltage drops below the undervoltage threshold or rises above the overvoltage threshold, the gate outputs are switched LOW in order to switch off the external MOSFETs. When the supply returns to a level that is above the UV threshold or below the OV threshold, the device resumes normal operation according to the established condition of the input terminals.
GLOBAL ENABLE (G_EN)
The G_EN terminal is used to place the device in a sleep mode. When the G_EN terminal voltage is a logic LOW state, the device is in sleep mode. The device is enabled and fully operational when the G_EN terminal voltage is logic HIGH, typically 5.0 V.
CHARGE PUMP OUT (CP_OUT)
The CP_OUT terminal is used to connect an external reservoir capacitor for the charge pump.
CHARGE PUMP CAPACITOR TERMINALS (C1 AND C2)
The C1 and C2 terminals are used to connect an external capacitor for the charge pump.
INPUT HIGH- AND LOW-SIDE TERMINALS (IN_HS1, IN_HS2, AND IN_LS1, IN_LS2)
The IN_HSn and IN_LSn terminals are input control terminals used to control the gate outputs. These terminals are 5.0 V CMOS-compatible inputs with hysteresis. IN_HSn and IN_LSn independently control GATE_HSn and GATE_LSn, respectively. During wake-up, the logic is supplied from the G_EN terminal. There is no internal circuit to prevent the external high-side and low-side MOSFETs from conducting at the same time.
LINEAR REGULATOR OUTPUT (LR_OUT)
The LR_OUT terminal is the output of the internal regulator. It is used to connect an external capacitor.
GROUND TERMINALS (GND_A, GND1 AND GND2)
These terminals are the ground terminals of the device. They should be connected together with a very low impedance connection.
SOURCE OUTPUT HIGH-SIDE TERMINALS (SRC_HS1 AND SRC_HS2)
The SRC_HSn terminals are the sources of the external high-side MOSFETs. The external high-side MOSFETs are controlled using the IN_HSn inputs.
GATE HIGH- AND LOW-SIDE TERMINALS (GATE_HS1, GATE_HS2, AND GATE_LS1, GATE_LS2)
The GATE_HSn and GATE_LSn terminals are the gates of the external high- and low-side MOSFETs. The external high- and low-side MOSFETs are controlled using the IN_HSn and IN_LSn inputs.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL TERMINAL DESCRIPTION
Table 5. Functional Truth Table
Conditions Sleep Normal Normal Undervoltage G_EN 0 1 1 1 IN_HSn x 1 0 x IN_LSn x 1 0 x Gate_HSn 0 1 0 0 Gate_LSn 0 1 0 0 Comments Device is in Sleep mode. The gates are at low state. Normal mode. The gates are controlled independently. Normal mode. The gates are controlled independently. The device is currently in fault mode. The gates are at low state. Once the fault is removed, the 33883 recovers its normal mode. The device is currently in fault mode. The gates are at low state. Once the fault is removed, the 33883 recovers its normal mode. The device is currently in fault mode. The high-side gate is at low state. Once the fault is removed, the 33883 recovers its normal mode. The device is currently in fault mode. The low-side gate is at low state. Once the fault is removed, the 33883 recovers its normal mode.
Overvoltage
1
x
x
0
0
Overtemperature on High-Side Gate Driver Overtemperature on Low-Side Gate Driver x = Don't care.
1
1
x
0
x
1
x
1
x
0
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FUNCTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION
DRIVER CHARACTERISTICS
Figure 5 represents the external circuit of the high-side gate driver. In the schematic, HSS represents the switch that is used to charge the external high-side MOSFET through the GATE_HS terminal. LSS represents the switch that is used to discharge the external high-side MOSFET through the GATE_HS terminal. A 180K internal typical passive discharge resistance and a 18 V typical protection zener are in parallel with LSS. The same schematic can be applied to the external low-side MOSFET driver simply by replacing terminal CP_OUT with terminal LR_OUT, terminal GATE_HS with terminal GATE_LS, and terminal SRC_HS with GND.
The different voltages and current of the high-side gate driver are illustrated in Figure 6. The output driver sources a peak current of up to 1.0 A for 200 ns to turn on the gate. After 200 ns, 100 mA is continuously provided to maintain the gate charged. The output driver sinks a high current to turn off the gate. This current can be up to 1.0 A peak for a 100 nF load.
IN_HS1
0 HSSpulse_IN
0 CP_OUT HSS DC_IN HSS IGATE_HS HSSDC_IN Icharge HSS Idischarge LSS Icharge HSS GATE_HS1 LSS_IN 0
IN_HS1 HSSpulse_IN LSS_IN
LSS
180 k 18V
1.0 A Peak 100 mA Typical 0
Idischarge LSS SRC_HS1 0
1.0 A Peak
Figure 5. High-Side Gate Driver Functional Schematic
IGATE_HS
1.0 A Peak 100 mA Typical 0 -1.0 A Peak
Note GATE_HS is loaded with a 100 nF capacitor in the chronograms. A smaller load will give lower peak and DC charge or discharge currents.
Figure 6. High-Side Gate Driver Chronograms
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
OPERATIONAL MODES TURN-ON
For turn-on, the current required to charge the gate source capacitor Ciss in the specified time can be calculated as follows: I P = Qg / t r = 80 nC / 80 ns 1.0 A Where Q g is power MOSFET gate charge and t r is peak current for rise time.
TURN-OFF
The peak current for turn-off can be obtained in the same way as for turn-on, with the exception that peak current for fall time, tf, is substituted for tr: I P = Qg /t f = 80 nC / 80 ns 1.0 A In addition to the dynamic current required to turn off or on the MOSFET, various application-related switching scenarios must be considered. These scenarios are presented in Figure 7. In order to withstand high dV/dt spikes, a low resistive path between gate and source is implemented during the OFF-state.
Flyback spike charges lowside gate via Crss charge current Irss up to 2.0 A. Causes increased uncontrolled turn-on of low-side MOSFET. VBAT
Flyback spike pulls down high-side source VGS. Delays turn-off of highside MOSFET.
Flyback spike charges lowside gate via Crss charge current Irss up to 2.0 A. Delays turn-off of low-side MOSFET.
Flyback spike pulls down high-side source VGS. Causes increased uncontrolled turn-on of high-side
Crss
Crss
VBAT
Crss OFF
VBAT OFF VGATE -VDRN
Crss
VBAT
GATE_HS Ciss Irss VGATE GATE_LS OFF Ciss Crss
GATE_HS ILOAD L1 Ciss Crss
GATE_HS ILOAD L1 Ciss Crss
GATE_HS ILOAD L1 Ciss Crss
L1
ILOAD
GATE_LS OFF Ciss
GATE_LS Ciss
GATE_LS Ciss
Driver Requirement: Low Resistive GateSource Path During OFF-State
Driver Requirement: Low Resistive GateSource Path During OFF-State. High Peak Sink Current Capability
Driver Requirement: High Peak Sink Current Capability
Driver Requirement: Low Resistive GateSource Path During OFF-State
Figure 7. OFF-State Driver Requirement
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
LOW-DROP LINEAR REGULATOR
The low-drop linear regulator is supplied by VCC2. If VCC2 exceeds 15.0 V, the output is limited to 14.5 V (typical). The low-drop linear regulator provides the 5.0 V for the logic section of the driver, the Vgs_ls buffered at LR_OUT, and the +14.5 V for the charge pump, which generates the CP_OUT The low-drop linear regulator provides 4.0 mA average current per driver stage. In case of the full bridge, that means approximately 16 mA -- 8.0 mA for the high side and 8.0 mA for the low side. Note: The average current required to switch a gate with a frequency of 100 kHz is: ICP = Qg * f PWM = 80 nC * 100 kHz = 8.0 mA In a full-bridge application only one high side and one low side switches on or off at the same time.
capacitor CCP_OUT provides peak current to the high-side MOSFET through HSS during turn-on (3).
VLR_OUT VLR-OUT
Tosc2 Tosc2 Ccp CCP CP_out CP_OUT D1 D1
CCP_OUT Ccp_out
C1 C1 Tosc1 Tosc1
C2 C2
D2 D2
Vcc VCC
T1 HSS
(3)
GATE_HS
GATE_HS
CHARGE PUMP
The charge pump generates the high-side driver supply voltage (CP_OUT), buffered at CCP_OUT. Figure 8 shows the charge pump basic circuit without load.
LSS
T2
Rg Rg
High-Side MOSFET
HS MOSFET
SRC_HS SRC_HS
(2)
D1 D1
VCP_OUT CP_OUT
Low-Side MOSFET MOSFET
LS
VLR_OUT VLR_OUT
Ccp CCP
C1
Osc. OSC.
A C2 D2 D2
(1)
Ccp_out CCP_OUT
Terminals pins
Figure 9. High-Side Gate Driver
Vbat VCC
Figure 8. Charge Pump Basic Circuit When the oscillator is in low state [(1) in Figure 8], CCP is charged through D2 until its voltage reaches VCC - VD2. When the oscillator is in high state (2), CCP is discharged though D1 in CCP_OUT, and final voltage of the charge pump, VCP_OUT, is Vcc + VLR_OUT - 2VD. The frequency of the 33883 oscillator is about 330 kHz.
EXTERNAL CAPACITORS CHOICE
External capacitors on the charge pump and on the linear regulator are necessary to supply high peak current absorbed during switching. Figure 9 represents a simplified circuitry of the high-side gate driver. Transistors Tosc1 and Tosc2 are the oscillatorswitching MOSFETs. When Tosc1 is on, the oscillator is at low level. When Tosc2 is on, the oscillator is at high level. The
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
CCP
CCP choice depends on power MOSFET characteristics and the working switching frequency. Figure 10 contains two diagrams that depict the influence of CCP value on VCP_OUT average voltage level. The diagrams represent two different frequencies for two power MOSFETs, MTP60N06HD and MPT36N06V.
CCP_OUT
Figure 11 depicts the simplified CCP_OUT current and voltage waveforms. fPWM is the working switching frequency.
Oscillator Oscillator in High in high Oscillator State Oscillator state in Low in low State state
High Side High Side Turn On turn on
VCP_OUT V Cp_out
rage V Cp_out Average VCP_OUT
VCP_OUT VCcp _ out
21 20.5
20 kHz 20KhZ 100 kHz 100 KhZ
ICP_OUT I
Cp_out
VVcp_out (v) CP_OUT (V)
20 19.5 19 18.5 18 5 25 45 65 85
f=330kHz f = 330 kHz
ffPWM PWM
Peak Peak Current Current
CCP(nF) Ccp (nF)
MTP60N06HD (Qg=50nC) MTP60N06HD (Qg = 50 nC)
Figure 11. Simplified CCP_OUT Current and Voltage Waveforms As shown above, at high-side MOSFET turn-on VCP_OUT voltage decreases. This decrease can be calculated according to the CCP_OUT value as follows: VCP_OUT = Qg CCP_OUT
MTP60N06HD (Qg = 50 nC)
21.5 21 Vcp_out (V)(V) VCP_OUT 20.5 20 19.5 19 18.5 5 20 kHz 100 kHz
Where Qg is power MOSFET gate charge.
CLR_OUT
CLR_OUT provides peak current needed by the low-side MOSFET turn-on. VLR_OUT decrease is as follows:
25 45 65 85
CCP (nF) Ccp (nF) MTP36N06V (Qg = 40 nC) Figure 10. VCP_OUT Versus CCP The smaller the CCP value is, the smaller the VCP_OUT value is. Moreover, for the same CCP value, when the switching frequency increases, the average VCP_OUT level decreases. For most of the applications, a typical value of 33 nF is recommended.
VLR_OUT =
Qg CLR_OUT
TYPICAL VALUES OF CAPACITORS
In most working cases the following typical values are recommended for a well-performing charge pump: CCP = 33 nF, CCP_OUT = 470 nF, and CLR_OUT = 470 nF These values give a typical 100 mV voltage ripple on VCP_OUT and VLR_OUT with Qg = 50 nC.
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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES
PROTECTION AND DIAGNOSTIC FEATURES GATE PROTECTION
The low-side driver is supplied from the built-in low-drop regulator. The high-side driver is supplied from the internal charge pump buffered at CP_OUT. The low-side gate is protected by the internal linear regulator, which ensures that VGATE_LS does not exceed the maximum VGS. Especially when working with the charge pump, the voltage at CP_OUT can be up to 65 V. The highside gate is clamped internally in order to avoid a VGS exceeding 18 V. Gate protection does not include a fly-back voltage clamp that protects the driver and the external MOSFET from a flyback voltage that can occur when driving inductive load. This fly-back voltage can reach high negative voltage values and needs to be clamped externally, as shown in Figure 12.
LR_OUT CP_OUT M1 IN OUT Output Driver GATE_HS VGS < 14 V SRC_HS Dc l M2 IN OUT Output Driver GATE_LS L1 Under All Conditions Inductive Flyback Voltage Clamp VCC
LOAD DUMP AND REVERSE BATTERY
VCC and VCC2 can sustain load a dump pulse of 40 V and double battery of 24 V. Protection against reverse polarity is ensured by the external power MOSFET with the freewheeling diodes forming a conducting pass from ground to VCC. Additional protection is not provided within the circuit. To protect the circuit an external diode can be put on the battery line. It is not recommended putting the diode on the ground line.
TEMPERATURE PROTECTION
There is temperature shutdown protection per each halfbridge. Temperature shutdown protects the circuitry against temperature damage by switching off the output drivers. Its typical value is 175C with an hysteresis of 15C.
DV/DT AT VCC
VCC voltage must be higher than (SRC_HS voltage minus a diode drop voltage) to avoid perturbation of the high-side driver. In some applications a large dV / dt at terminal C2 owing to sudden changes at VCC can cause large peak currents flowing through terminal C1, as shown in Figure 13. For positive transitions at terminal C2, the absolute value of the minimum peak current, I C1min, is specified at 2.0 A for a t C1min duration of 600 ns. For negative transitions at terminal C2, the maximum peak current, IC1max, is specified at 2.0 A for a t C1max duration of 600 ns. Current sourced by terminal C1 during a large dV / dt will result in a negative voltage at terminal C1 (Figure 13). The minimum peak voltage VC1min is specified at -1.5 V for a duration of t C1max = 600 ns. A series resistor with the charge pump capacitor (Ccp) capacitor can be added in order to limit the surge current.
Figure 12. Gate Protection and Flyback Voltage Clamp
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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES
VCC
IC1max
t C1min
I (C1+C2)
0A
t C1max
I C1min
V(LR_OUT)
V(C1)
0V
VC1min
Figure 13. Limits of C1 Current and Voltage with Large Values of dV/dt In the case of rapidly changing VCC voltages, the large dV/ dt may result in perturbations of the high-side driver, thereby forcing the driver into an OFF state. The addition of capacitors C3 and C4, as shown in Figure 14, reduces the dV/dt of the source line, consequently reducing driver perturbation. Typical values for R3 / R4 and C3 / C4 are 10 and 10 nF, respectively.
DV/DT AT VCC2
When the external high-side MOSFET is on, in case of rapid negative change of VCC2 the voltage (VGATE_HS VSRC_HS) can be higher than the specified 18 V. In this case a resistance in the SRC line is necessary to limit the current to 5.0 mA max. It will protect the internal zener placed between GATE_HS and SRC terminals. In case of high current (SRC_HS >100 mA) and high voltage (>20 V) between GATE_HSX and SRC_HS an external zener of 18 V is needed as shown in Figure 14.
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
VBAT VBOOST
VCC VCC2 G_EN CCP
33 nF
33883 VCC VCC2 G_EN C1 C2 IN_HS1 CP_OUT LR_OUT CCP_OUT 470 nF CLR_OUT 470 nF 18 V R3 10 C3 10 nF M1 R1 R2 50 R4 10 C4 10 nF M3
50
C1 C2 IN_HS1 IN_LS1 IN_HS2 IN_LS2
GATE_HS1 SRC_HS1 GATE_LS1 GATE_HS2
MCU
DC Motor
IN_LS1 SRC_HS2 IN_HS2 GATE_LS2 IN_LS2 GND
18 V 50
M2 50
M4
Figure 14. Application Schematic with External Protection Circuit
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PACKAGING PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below.
DW SUFFIX EG SUFFIX (PB-FREE) 20-TERMINAL SOICW PLASTIC PACKAGE 98ASB42343B ISSUE J
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Analog Integrated Circuit Device Data Freescale Semiconductor
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REVISION HISTORY PACKAGING DIMENSIONS
REVISION HISTORY
REVISION 9.0
DATE 1/2007
DESCRIPTION OF CHANGES * * * * * Implemented Revision History page Updated to the current Freescale format and style Added MCZ33883EG/R2 to the Ordering Information Updated the package drawing to Rev. J Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from MAXIMUM RATINGS on page 4. Added note with instructions from www.freescale.com.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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MC33883 Rev 9.0 1/2007

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